1. Field of the Invention
Embodiments of the present invention relate to semiconductor devices.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate in a stacked configuration. An edge view of a conventional semiconductor package 20 (without molding compound) is shown in prior art FIGS. 1 and 2. Typical packages include a plurality of semiconductor die 22, 24 mounted to a substrate 26. Although not shown in FIGS. 1 and 2, the semiconductor die are formed with die bond pads on an upper surface of the die. Substrate 26 may be formed of an electrically insulating core sandwiched between upper and lower conductive layers. The upper and/or lower conductive layers may be etched to form conductance patterns including electrical leads and contact pads. Wire bonds are soldered between the die bond pads of the semiconductor die 22, 24 and the contact pads of the substrate 26 to electrically couple the semiconductor die to the substrate. The electrical leads on the substrate in turn provide an electrical path between the die and a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
It is known to layer semiconductor die on top of each other either with an offset (prior art FIG. 1) or in a stacked configuration (prior art FIG. 2). In the offset configuration of FIG. 1, the die are stacked with an offset so that the bond pads of the next lower die are left exposed. The offset requires a greater footprint on the substrate, where space is at a premium. In the stacked configuration of FIG. 2, two or more semiconductor die are stacked directly on top of each other, thereby taking up less footprint on the substrate as compared to an offset configuration. However, in a stacked configuration, space must be provided between adjacent semiconductor die for the bond wires 30. In addition to the height of the bond wires 30 themselves, additional space must be left above the bond wires, as contact of the bond wires 30 of one die with the next die above may result in an electrical short. As shown in FIG. 2, it is therefore known to provide a dielectric spacer layer 34 to provide enough room for the bond wires 30 to be bonded to the die bond pad on the lower die 24.
As electronic components get smaller and operate at higher frequencies, the noise and cross talk caused by electromagnetic interference (EMI) and radiofrequency interference (RFI) is becoming more of a concern. EMI is the induction of electromagnetic radiation, which is emitted by electrical circuits carrying rapidly changing signals, as a by-product of their normal operation to other circuits which causes unwanted signals (interference or noise). RFI is transmission of radiofrequency electromagnetic radiation from one circuit to another, also causing unwanted interference or noise.
Some semiconductor packages have attempted to shield the transmission and receipt of EMI and RFI radiation at the semiconductor package level. While preventing interference, these conventional solutions have other disadvantages which make inclusion of such features at the package level undesirable. Thus, shielding is typically performed at the host device level in which a semiconductor package is used. Host device level solutions typically involve providing a metal shield around the space where a semiconductor package is received or mounted.